The present invention relates to metallization processing for integrated circuit semiconductor device and circuit board manufacture, and is especially adapted for use in processing employing "damascene" (or "in-laid") technology.
The escalating requirements for high density and performance associated with ultra large scale integration (ULSI) semiconductor device wiring are difficult to satisfy in terms of providing submicron-sized (e.g., 0.18 .mu.m and below, such as 0.15 .mu.m and below), low resistance-capacitance (RC) time constant metallization patterns, particularly wherein the submicron-sized metallization features such as vias, contact areas, grooves, trenches, etc., have high aspect (i.e., depth-to-width) ratios due to microminiaturization.
Semiconductor devices of the type contemplated herein typically comprise a semiconductor wafer substrate, usually of doped monocrystalline silicon, and a plurality of sequentially formed inter-layer dielectrics and conductive patterns formed therein and/or therebetween. An integrated circuit is formed therefrom containing a plurality of patterns of conductive lines separated by interwiring spacings, and a plurality of interconnect lines, such as bus lines, bit lines, word lines, and logic interconnect lines. Typically, the conductive patterns of vertically spaced apart metallization layers are electrically connected by a vertically oriented conductive plug filling a via hole formed in the dielectric layer separating the layers, while another conductive plug filling a contact area hole establishes electrical contact with an active region, such as a source/drain region, formed in or on the semiconductor substrate. Conductive lines formed in groove or trench-like openings in overlying dielectric layers extend substantially parallel to the semiconductor substrate. Semiconductor devices of such type fabricated according to current technology may comprise five or more layers of such metallization in order to satisfy device geometry and miniaturization requirements.
Electrically conductive films or layers of the type contemplated herein for use in e.g., "back-end" semiconductor manufacturing technology as required for fabrication of devices as above described typically comprise a metal such as titanium, tantalum, tungsten, aluminum, chromium, nickel, cobalt, silver, gold, copper, and their alloys. In use, each of the recited metals presents advantages as well as drawbacks. For example, aluminum (Al) is relatively inexpensive, exhibits low resistivity, and is relatively easy to etch. However, in addition to being difficult to deposit by lower cost, lower temperature, more rapid "wet" technology such as electrodeposition, step coverage with Al is poor when the metallization features are scaled down to sub-micron size, resulting in decreased reliability of interconnections, high current densities at certain locations, and increased electromigration. In addition, low dielectric constant materials, e.g., polyimides, when employed as inter-layer dielectrics, create moisture/bias reliability problems when in contact with Al.
The use of via plugs filled with tungsten (W) may alleviate several problems associated with Al. However, most W-based processes are complex and expensive. In addition, the high resistivity of W may cause Joule heating which can undesirably enhance electromigration of Al in adjacent wiring. Moreover, W plugs are susceptible to void formation and high contact resistance at the interface with the Al wiring layer.
Copper (Cu) and Cu-based alloys are particularly attractive, as for use in ULSI devices requiring multilevel metallization systems for "back-end" processing of the semiconductor wafers. Cu and Cu-based metallization systems have very low resistivities, i.e., significantly lower than that of W and even lower than those of previously preferred systems utilizing Al and its alloys, as well as significantly higher resistance to electromigration. Moreover, Cu and its alloys enjoy a considerable cost advantage over a number of the above-enumerated metals, notably silver and gold. Also, in contrast to Al and the refractory-type metals, Cu and its alloys can be readily deposited at low temperatures in good quality, bright layer form by well-known electroplating techniques, at deposition rates fully compatible with the requirements of device manufacturing throughput.
In addition to convenient, relatively low cost, low temperature, high throughput "wet" deposition by electroplating, Cu and its alloys are readily amenable to low cost, high throughput electroless deposition of high quality films for efficiently filling recesses such as vias, contact areas, and grooves and trenches forming interconnection routing. Such electroless plating generally involves the controlled autocatalytic deposition of a continuous film of Cu or an alloy thereof on a catalytic surface by the interaction of at least a Cu-containing salt and a chemical reducing agent contained in a suitable solution, whereas electroplating comprises employing electrons supplied to an electrode from an external source (i.e., a power supply) for reducing Cu ions in solution and depositing reduced metal atoms on the surface thereof. In either case, a nucleation/seed layer is required for catalysis and/or deposition on the types of substrates contemplated for use herein. Finally, while electroplating requires a continuous nucleation/seed layer, very thin and discontinuous islands of a catalytic metal may be employed with electroless plating.
As indicated above, a commonly employed method for forming "in-laid" metallization patterns such as are required for "back-end" metallization processing of semiconductor wafers employs "damascene" type technology. Generally, in such processing methodology, a recess (i.e., an opening) for forming, e.g., a via hole in an inter-layer dielectric for electrically connecting vertically separated metallization layers, is created in the inter-layer dielectric by conventional photolithographic and etching techniques, and filled with a metal plug, typically of W. Any excess conductive material (i.e., W) on the surface of the dielectric interlayer is then removed by, e.g., chemical-mechanical polishing techniques (CMP), wherein a moving pad is biased against the surface to be polished, with the interposition of a slurry containing abrasive particles (and other ingredients) therebetween. A variant of the above-described technique, termed "dual damascene" processing, involves the formation of an opening comprising a lower contact or via hole section in communication with an upper groove or trench section, which opening is filled with a conductive material, typically a metal, to simultaneously form a conductive plug in electrical contact with a conductive line.
Referring now to FIG. 1, schematically shown therein in simplified cross-sectional view is a conventional damascene processing sequence employing relatively low cost, high manufacturing throughput electroplating and CMP techniques for forming recessed "back-end" metallization patterns (illustratively of Cu-based metallurgy but not limited thereto) in a semiconductor device formed in or on a semiconductor wafer substrate 1. In a first step, the desired arrangement of conductors is defined as a pattern of recesses 2 such as via holes, grooves, trenches, etc., formed (as by conventional photolithographic and etching techniques) in the surface 4 of a dielectric layer 3 (e.g., a silicon oxide and/or nitride or an organic polymeric material) deposited or otherwise formed over the semiconductor substrate 1. In a second step, a layer of Cu or Cu-based alloy 5 is deposited by conventional electroplating techniques to fill the recesses 2. In order to ensure complete filling of the recesses, the Cu-containing layer is deposited as a blanket (or "overburden") layer of excess thickness t so as to overfill the recesses 2 and cover the upper surface 4 of the dielectric layer 3. Next, the entire excess thickness t of the metal overburden layer 5 over the surface 4 of the dielectric layer 3 is removed by a CMP process utilizing an alumina-based slurry, leaving metal portions 5' in the recesses 2 with their exposed upper surfaces 6 substantially coplanar with the surface 4 of the dielectric layer 3.
The above-described conventional damascene process forms in-laid conductors 5' in the dielectric layer 3 while avoiding problems associated with other types of metallization patterning processing, e.g., blanket metal layer deposition, followed by photolithographic masking/etching and dielectric gap filling. In addition, such single or dual damascene-type processing can be performed with a variety of other types of substrates, e.g., printed circuit boards, with and/or without intervening dielectric layers, and with a plurality of metallization levels, i.e., five or more levels.
However, the use of electroplated metallization as described above has presented a number of problems, particularly, but not exclusively, with the use of Cu-based metallurgy. For example, although electroplating of Cu (a "wet" technique) has advantages over "dry" techniques (e.g., physical or chemical vapor deposition), such as rapid rates of deposition at low temperatures and good compatibility with "wet" CMP processing, it suffers from a drawback of ridge build-up over sharp corners of vias, grooves, and trenches. Thus, in conventional practices utilizing electrolytic deposition of Cu or Cu-based alloy conductors, a rather thick blanket or overburden layer 5, typically about 0.5-1.5 .mu.m thick, must be deposited over the recess-patterned surface to ensure complete filling (i.e., overfilling) of recesses 2 such as via holes, trenches, grooves, and other variously configured openings. Moreover, the resulting surface after overfilling may be highly non-planar, with the layer thicknesses thereof spanning the entire range of thicknesses given above.
Removal of such thick, non-planar blanket layers of Cu-based material in the subsequent CMP step for planarizing the interconnection metallization entails a number of disadvantages. For example, removal of the excess Cu-based material by CMP is slow and expensive. Specifically, typical Cu or Cu-based alloy removal rates by CMP employing a conventional alumina-based slurry are on the order of about 2,000-3,000 .ANG./min. Consequently, removal of 0.5-1.5 .mu.m thick Cu-based layers can require long processing times extending up to about 5 minutes, considerably longer than that desired for good manufacturing throughput and reduced expense. In addition, removal of such thick as-deposited Cu or Cu-based alloy blanket or overburden layers by CMP results in less uniform polished layers as are obtained when CMP is performed on thinner deposited layers. Such poor uniformity is generally accompanied by an increase in defects such as non-planarity ("dishing") and gouging ("erosion") between adjacent metallization lines.
A further drawback associated with Cu-based "back-end" metallization is the possibility of Cu diffusion into the underlying semiconductor, typically silicon, resulting in degradation of the semiconductive properties thereof, as well as poor adhesion of the deposited Cu or Cu-based alloy layer to various materials employed as inter-layer dielectrics, etc. As a consequence of these phenomena associated with Cu-based metallurgy, it is generally necessary to provide an adhesion promoting and/or diffusion barrier layer intermediate to the semiconductor substrate and the overlying Cu-based metallization layer. Suitable materials for such adhesion/barrier layers include, e.g., chromium (Cr), tantalum (Ta), and tantalum nitride (TaN).
Yet another drawback associated with the use of electroplated Cu or Cu-based alloy damascene type metallization arises from incomplete filling of the recesses during the electroplating process, resulting in void and/or other defect formation causing a reduction in device quality. While the exact mechanism of such void formation due to premature occlusion or "pinching-off" of recesses at the upper, or mouth portions thereof is not known with certainty, it is believed to result from formation of overhanging portions of the adhesion/barrier and/or nucleation/seed layers at the upper corners of the recesses during the physical vapor deposition (PVD) processing utilized for their deposition, as well as from increased rates of Cu electroplating at the corners of the adhesion/barrier and/or nucleation/seed layers. It is further believed that such increased rates of deposition at the corners are related to the formation of higher electric fields thereat during application of the electrical potentials necessary for effecting electroplating thereon.
A still further drawback attendant upon the use of damascene technology for forming sub-micron dimensioned in-laid metallization patterns and features arises from the loss of critical dimension (CD) of the hardmask utilized in the step for forming the pattern of recesses in the dielectric layer according to conventional reactive ion etching processing for obtaining the requisite anisotropic etching of the dielectric layer, resulting in an undesirable increase in recess opening and other feature dimensions. Adverting to FIGS. 2(A)-2(C), shown therein in simplified, cross-sectional schematic form, are views successively illustrating initial, intermediate, and final stages of a conventional reactive ion etching process for forming sub-micron-dimensioned recesses in a dielectric layer, utilizing a silicon nitride hard mask.
Referring more particularly to FIG. 2(A), in a first step, a layer 7 of silicon nitride hardmask material is formed over the exposed upper surface 4 of dielectric layer 3 formed on the upper surface of substrate 1, typically a semiconductor wafer comprising at least one active device region formed therein or thereon and patterned, as by conventional photolithographic masking and etching techniques employing a layer of photoresist material, to form a sub-micron-dimensioned mask opening 8 therein having a critical dimension CD. The substrate having the patterned mask thereon is then subjected to conventional reactive ion etching, typically selected from DC, RF, and directed beam reactive ion etching utilizing a fluorine-containing plasma, for forming a recess 2 in the surface 4 of dielectric layer 3. FIG. 2(B) illustrates the etch profiles approximately halfway through the etching process. As shown therein, relatively small portions 7' (represented by dashed lines in the figure) of the silicon nitride hardmask layer 7 bordering mask opening 8 have been lost (i.e., consumed) due to sputtering therefrom which is incidental to the reactive ion etching process, and, as a consequence, sidewalls 2' of recess 2 have begun to exhibit slight to moderate inwardly tapering, i.e., a small deviation from perpendicularity with upper surface 4 of dielectric layer 3. However, at the completion of the etching process, as shown in FIG. 2(C), relatively large portions 7" (again represented by dashed lines in the figure) have been lost or consumed due to sputtering therefrom and the inward tapering of recess sidewalls 2' is substantial, resulting in significant loss in CD and undesirable increase in recess dimensions, particularly at the mouth portion thereof adjacent upper surface 4 of dielectric layer 3. Thus, it is apparent that the CD cannot be adequately maintained during recess formation according to the conventional reactive ion etching processing. In addition to the loss of CD, the use of a high dielectric constant hardmask material (e.g., silicon nitride) can undesirably add to device capacitance if it is allowed to remain on the wafer as a "sandwich" dielectric. As a consequence, an additional processing step, e.g., plasma etching, may be required to remove such hardmask material prior to filling the recesses with conductive material, as by electroplating.
As design rules extend further into the submicron range, e.g., about 0.18 .mu.m and below, such as 0.15 .mu.m and below, and the number of metallization levels increases, maintenance of the critical feature sizes or dimensions of the metallization/interconnect pattern becomes increasingly important. Accordingly, the problem of increased feature size resulting from undesired coincidental sputtering of the hardmask causing loss of the CD during recess formation in the dielectric layer requires resolution.
Thus, there exists a need for metallization methodology enabling the formation of submicron-dimensioned metal contact and interconnect members, particularly of Cu or Cu-based alloys, having desired feature sizes, high reliability, high yield, and high performance. In particular, there exists a need for eliminating the problem of loss of CD during formation of sub-micron-dimensioned recesses which are subsequently filled by conventional electroplating techniques.
The present invention addresses and solves the problems attendant upon conventional processes for manufacturing semiconductor devices utilizing electroplated Cu or Cu-based alloy metallization, particularly in the formation of in-laid "back-end" contacts/metallization patterns by damascene techniques employing electroplating and CMP for obtaining good manufacturing throughput and product quality.